SPI0 control clear register. Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared.
| RXTHINTCLR | Receive FIFO Threshold Interrupt clear. |
| RESERVED | Writing ones to this register clears the corresponding bit or bits in the CTLSETSPI register, if they are implemented. Bits that do not correspond to defined bits in CTLSETSPI are reserved and only zeroes should be written to them. |
| TXTHINTCLR | Transmit FIFO Threshold Interrupt clear. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| RXTIMEOUTINTCLR | Receive FIFO Timeout Interrupt clear. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| RXFLUSHCLR | Receive FIFO flush clear. do the clear bits 8 and 9 do anything? |
| TXFLUSHCLR | Transmit FIFO flush clear. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |